Power supply voltage transition comparison circuit, power supply voltage transition comparison method, and semiconductor integrated circuit

ABSTRACT

A power supply voltage transition comparison circuit includes a comparator evaluation voltage setting circuit that generates a divided voltage of a power supply voltage; a comparator that compares a reference voltage with the divided voltage; a voltage evaluation circuit that evaluates the power supply voltage based on a result of the comparison; and an evaluation voltage setting value output circuit that changes a ratio between the power supply voltage and the divided voltage based on a result of an evaluation of the power supply voltage.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a Continuation Application of U.S. patentapplication Ser. No. 14/303,424, filed on Jun. 12, 2014, which is basedon Japanese Patent Application No. 2013-148541, filed on Jul. 17, 2013,the entire contents of which are hereby incorporated by reference.

BACKGROUND

The present invention relates to a power supply voltage transitioncomparison circuit, a power supply voltage transition comparison method,and a semiconductor integrated circuit. For example, the presentinvention relates to a power supply voltage transition comparisoncircuit suitable for use in which a semiconductor integrated circuit isset to a test mode, a power supply voltage transition comparison methodsuitable for that use, and a semiconductor integrated circuit includingthe power supply voltage transition comparison circuit.

Test signal generation circuits for generating a test signal for settinga semiconductor integrated circuit such as a microcontroller to a testmode have been known. For example, a test signal generation circuit of asemiconductor device disclosed in Japanese Unexamined Patent ApplicationPublication No. 4-147074 includes a high-voltage detection circuit, acounter, and a test signal latch. The high-voltage detection circuitdetermines whether or not a voltage higher than a normal power supplyvoltage is input to a first input terminal. The counter counts a clocksignal that is input to a second input terminal while the voltage higherthan the normal power supply voltage is input to the first inputterminal. The test signal latch generates a test signal when the countnumber of the counter reaches a predetermined count number.

A test signal generation circuit of a semiconductor device disclosed inJapanese Unexamined Patent Application Publication No. 6-207971 includesa high-voltage detection circuit, a counter, and a test signal latchcircuit. The high-voltage detection circuit determines whether or not avoltage higher than a normal power supply voltage is input to an inputterminal, and outputs a high-voltage detection signal. The countercounts the high-voltage detection signal. The test signal latch circuitgenerates a test signal when the count number of the counter reaches apredetermined count number.

A test signal generation circuit disclosed in Japanese Unexamined PatentApplication Publication No. 6-309475 includes first to third voltagecomparators and a combinational logic circuit that logically processesthe outputs of these comparators. The first voltage comparator comparesa power supply voltage with a first reference voltage. The secondvoltage comparator compares the power supply voltage with a secondreference voltage. The third voltage comparator compares the powersupply voltage with a third reference voltage. The first referencevoltage is higher than the second reference voltage, and the secondreference voltage is higher than the third reference voltage. When thecombinational logic circuit detects an output pattern that is outputfrom the first to third comparators when a power supply voltage having apredetermined voltage waveform is input to the first to thirdcomparators, the combinational logic circuit generates a test signal.When the test signal is generated, the circuit(s) to be tested is set toa test mode.

SUMMARY

In the test signal generation circuits disclosed in Japanese UnexaminedPatent Application Publications No. 4-147074 and No. 6-207971, the inputvoltage to be evaluated is compared with one predetermined voltagelevel. The present inventor has found a problem that since the inputvoltage is compared with only one predetermined voltage level, it isdifficult to lower the probability of an accidental match between theinput voltage transition and the expected voltage transition that canlead to the generation of the test signal in the test signal generationcircuit.

In the test signal generation circuit disclosed in Japanese UnexaminedPatent Application Publication No. 6-3-09475, the power supply voltageto be evaluated is compared with a plurality of reference voltages. Theinventor has found out that it is possible to lower the probability ofan accidental match between the power supply voltage transition and theexpected voltage transition that can lead to the generation of the testsignal in the test signal generation circuit by increasing the number ofreference voltages. However, if the number of reference voltages isincreased in the test signal generation circuit, the number of voltagecomparators increases, thus increasing the circuit size.

The above and other aspects, advantages and features will be moreapparent from the following description of certain embodiments taken inconjunction with the accompanying drawings.

A first aspect of the present invention is a power supply voltagetransition comparison circuit that evaluates a power supply voltagebased on a result of a comparison between a divided voltage of one ofthe power supply voltage and a reference voltage and a voltage of theother of the power supply voltage and the reference voltage, and changesa ratio between the one voltage and the divided voltage based on aresult of an evaluation of the power supply voltage.

According to the above-described first aspect, it is possible to lowerthe probability of an accidental match between the power supply voltagetransition and the expected voltage transition while minimizing theincrease in the circuit size of the circuit that compares the powersupply voltage transition with the expected voltage transition.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, advantages and features will be moreapparent from the following description of certain embodiments taken inconjunction with the accompanying drawings, in which:

FIG. 1 is a circuit configuration diagram of a power supply voltagetransition comparison circuit according to a first embodiment;

FIG. 2 is a flowchart showing an operation of the power supply voltagetransition comparison circuit according to the first embodiment;

FIG. 3 is a timing chart showing an operation of the power supplyvoltage transition comparison circuit according to the first embodimentand a transition of a power supply voltage to be monitored;

FIG. 4 is a schematic diagram of a voltage evaluation circuit accordingto a modified example of the first embodiment;

FIG. 5 is a circuit configuration diagram of a power supply voltagetransition comparison circuit according to a second embodiment;

FIG. 6 is a table held by a transition number WAIT time setting circuitaccording to the second embodiment;

FIG. 7 is a table held by an expected voltage setting circuit accordingto the second embodiment;

FIG. 8 is a flowchart showing an operation of the power supply voltagetransition comparison circuit according to the second embodiment;

FIG. 9 is a circuit configuration diagram of a power supply voltagetransition comparison circuit according to a third embodiment;

FIG. 10 is a flowchart showing an operation of the power supply voltagetransition comparison circuit according to the third embodiment;

FIG. 11 is a timing chart showing an operation of the power supplyvoltage transition comparison circuit according to the third embodimentand a transition of a power supply voltage to be monitored;

FIG. 12 is a circuit configuration diagram of a power supply voltagetransition comparison circuit according to a fourth embodiment; and

FIG. 13 is a schematic diagram of a semiconductor integrated circuitaccording to a fifth embodiment.

DETAILED DESCRIPTION

Embodiments of a power supply voltage transition comparison circuit, apower supply voltage transition comparison method, a program of a methodfor controlling a power supply voltage transition comparison circuit,and a semiconductor integrated circuit are explained hereinafter withreference to the drawings. For clarifying the explanation, the followingdescriptions and the drawings may be partially omitted or simplified asappropriate. Further, the same symbols are assigned to the samecomponents throughout the drawings, and their duplicated explanation isomitted as necessary.

First Embodiment

FIG. 1 is a circuit configuration diagram of a power supply voltagetransition comparison circuit 20A according to a first embodiment. Thepower supply voltage transition comparison circuit 20A performs acomparison of a power supply voltage transition by determining whetheror not a transition of a power supply voltage PSV to be monitoredmatches an expected voltage transition. Note that the expected voltagetransition is a voltage transition that can generate a lock cancellationsignal LCS for the power supply voltage transition comparison circuit20A.

The power supply voltage transition comparison circuit 20A includes acomparator evaluation voltage setting circuit 5, comparators 3 and 4, avoltage evaluation circuit 8, and an evaluation voltage setting valueoutput circuit 7. The comparator evaluation voltage setting circuit 5generates an upper-limit comparison voltage UCV and a lower-limitcomparison voltage LCV as divided voltages of the power supply voltagePSV. The comparator 3 compares the upper-limit comparison voltage UCVwith a reference voltage RV1. The comparator 4 compares the lower-limitcomparison voltage LCV with the reference voltage RV1. The voltageevaluation circuit 8 evaluates the power supply voltage PSV based on theresult of the comparison between the upper-limit comparison voltage UCVand the reference voltage RV1 and the result of the comparison betweenthe lower-limit comparison voltage LCV and the reference voltage RV1.The evaluation voltage setting value output circuit 7 changes a ratio K1between the power supply voltage PSV and the upper-limit comparisonvoltage UCV, and a ratio K2 between the power supply voltage PSV and thelower-limit comparison voltage LCV based on the result of the evaluationof the power supply voltage PSV.

According to this embodiment, it is possible to increase the number ofexpected voltage levels, which are compared with the power supplyvoltage PSV, without increasing the number of comparators. This isbecause the ratio K1 between the power supply voltage PSV and theupper-limit comparison voltage UCV and the ratio K2 between the powersupply voltage PSV and the lower-limit comparison voltage LCV arechanged based on the result of the comparison between the upper-limitcomparison voltage UCV and the reference voltage RV1 and the result ofthe comparison result between the lower-limit comparison voltage LCV andthe reference voltage RV1. Therefore, it is possible to lower theprobability of an accidental match between the transition of the powersupply voltage PSV and the expected voltage transition while minimizingthe increase in the circuit size of the power supply voltage transitioncomparison circuit 20A. Therefore, it is possible to prevent an outsiderwho does not know the expected voltage transition from illegitimatelygenerating the lock cancellation signal LCS. Further, since the increasein the circuit size is minimized, the increase in the currentconsumption is also minimized.

Next, a configuration of the power supply voltage transition comparisoncircuit 20A is explained in detail.

The power supply voltage transition comparison circuit 20A includes apower supply to be monitored 1, a BGR (Band Gap Reference) circuit 2, acomparator 3, a comparator 4, a comparator evaluation voltage settingcircuit 5, an AND-gate having an inverter 6, an evaluation voltagesetting value output circuit 7, a voltage evaluation circuit 8, and avoltage evaluation control circuit 9.

The power supply to be monitored 1 (hereinafter called “monitored powersupply 1”) is, for example, a power supply terminal of a semiconductorcircuit in which the power supply voltage transition comparison circuit20A is provided. The monitored power supply 1 outputs a power supplyvoltage PSV to the BGR circuit 2 and the comparator evaluation voltagesetting circuit 5. The BGR circuit 2 is a reference voltage generationcircuit that generates a reference voltage RV1 from the power supplyvoltage PSV. The BGR circuit 2 keeps the reference voltage RV1 at apredetermined fixed voltage even when the power supply voltage PSVfluctuates. The BGR circuit 2 outputs the reference voltage RV1 to+input terminals of the comparators 3 and 4.

The comparator evaluation voltage setting circuit 5 includes resistancevoltage-dividing circuits 12 and 13. The resistance voltage-dividingcircuit 12 generates an upper-limit comparison voltage UCV from thepower supply voltage PSV and outputs the upper-limit comparison voltageUCV to a −input terminal of the comparator 3. The resistancevoltage-dividing circuit 13 generates a lower-limit comparison voltageLCV from the power supply voltage PSV and outputs the lower-limitcomparison voltage LCV to a −input terminal of the comparator 4. Theupper-limit comparison voltage UCV and the lower-limit comparisonvoltage LCV are divided voltages of the power supply voltage PSV. Thecomparator evaluation voltage setting circuit 5 sets a ratio K1 betweenthe power supply voltage PSV and the upper-limit comparison voltage UCVand a ratio K2 between the power supply voltage PSV and the lower-limitcomparison voltage LCV at the same time based on an evaluation voltagesetting signal DVS. Note that the evaluation voltage setting signal DVSindicates the upper-limit voltage and the lower-limit voltage of anexpected voltage range.

The comparator evaluation voltage setting circuit 5 sets the resistancevalue of the resistance voltage-dividing circuit 12 and thereby sets theratio K1 so that when the power supply voltage PSV matches theupper-limit voltage, the upper-limit comparison voltage UCV matches thereference voltage RV1. Further, the comparator evaluation voltagesetting circuit 5 sets the resistance value of the resistancevoltage-dividing circuit 13 and thereby sets the ratio K2 so that whenthe power supply voltage PSV matches the lower-limit voltage, thelower-limit comparison voltage LCV matches the reference voltage RV1.When the upper-limit voltage and the lower-limit voltage indicated bythe evaluation voltage setting signal DVS change, the comparatorevaluation voltage setting circuit 5 changes the ratios K1 and K2 sothat they conform to the new upper-limit voltage and lower-limitvoltage.

The comparator 3 performs a voltage upper-limit comparison. Thecomparator 3 compares the reference voltage RV1 input to the +inputterminal with the upper-limit comparison voltage UCV input to the −inputterminal and outputs a comparator output signal UCO, which is a digitalsignal indicating the comparison result, to an inverter-side inputterminal of the AND-gate having an inverter 6 (hereinafter called“inverter-equipped AND-gate 6”). The comparator output signal UCO is ata low level when the upper-limit comparison voltage UCV is lower thanthe reference voltage RV1. Further, the comparator output signal UCO isat a high level when the upper-limit comparison voltage UCV is higherthan the reference voltage RV1. In other words, when the power supplyvoltage PSV is lower than the upper-limit voltage indicated by theevaluation voltage setting signal DVS, the comparator output signal UCOis at a low level, whereas when the power supply voltage PSV is higherthan the upper-limit voltage indicated by the evaluation voltage settingsignal DVS, the comparator output signal UCO is at a high level.

The comparator 4 performs a voltage lower-limit comparison. Thecomparator 4 compares the reference voltage RV1 input to the +inputterminal with the lower-limit comparison voltage LCV input to the −inputterminal and outputs a comparator output signal LCO, which is a digitalsignal indicating the comparison result, to the other input terminal ofthe inverter-equipped AND-gate 6. The comparator output signal LCO is ata low level when the lower-limit comparison voltage LCV is lower thanthe reference voltage RV1. Further, the comparator output signal LCO isat a high level when the lower-limit comparison voltage LCV is higherthan the reference voltage RV1. In other words, when the power supplyvoltage PSV is lower than the lower-limit voltage indicated by theevaluation voltage setting signal DVS, the comparator output signal LCOis at a low level, whereas when the power supply voltage PSV is higherthan the lower-limit voltage indicated by the evaluation voltage settingsignal DVS, the comparator output signal LCO is at a high level.

The inverter-equipped AND-gate 6 outputs a logic gate output signal LGOto the voltage evaluation circuit 8 based on the comparator outputsignals UCO and LCO. The logic gate output signal LGO is at a high levelwhen the comparator output signal UCO is at a low level and thecomparator output signal LCO is at a high level. Further, the logic gateoutput signal LGO is at a low level in the other cases. That is, whenthe power supply voltage PSV is between the upper-limit voltage and thelower-limit voltage indicated by the evaluation voltage setting signalDVS, the logic gate output signal LGO is at a high level, whereas whenthe power supply voltage PSV is not between the upper-limit voltage andthe lower-limit voltage, the logic gate output signal LGO is at a lowlevel.

When the voltage evaluation circuit 8 receives a voltage evaluationimplementation instruction signal VDC from the voltage evaluationcontrol circuit 9, the voltage evaluation circuit 8 determines whetheror not the power supply voltage PSV is within the expected voltage rangeand outputs a voltage evaluation result signal VDR indicating theevaluation result to the voltage evaluation control circuit 9. When thelogic gate output signal LGO is at a high level, the voltage evaluationcircuit 8 determines that the power supply voltage PSV is within theexpected voltage range. When the logic gate output signal LGO is at alow level, the voltage evaluation circuit 8 determines that the powersupply voltage PSV is outside the expected voltage range.

The voltage evaluation control circuit 9 controls the overall sequencefor determining whether or not the transition of the power supplyvoltage PSV matches an expected voltage transition. The voltageevaluation control circuit 9 includes an evaluation step counter 10 anda WAIT counter 11. The evaluation step counter 10 counts the number ofevaluation steps. The voltage evaluation control circuit 9 outputs anevaluation step number signal DSN indicating the count value of theevaluation step counter 10 (evaluation step number) to the evaluationvoltage setting value output circuit 7. A plurality of count values thatthe evaluation step counter 10 can take correspond to a plurality ofrespective evaluation steps. Further, the voltage evaluation controlcircuit 9 secures a wait time (WAIT time) between evaluation steps byusing the WAIT counter 11.

The evaluation voltage setting value output circuit 7 holds a pluralityof setting value groups associated with the plurality of respectivecount values. Each setting value group includes an upper-limit voltageand a lower-limit voltage of an expected voltage range. The evaluationvoltage setting value output circuit 7 conveys the upper-limit voltageand the lower-limit voltage of an expected voltage range correspondingto a count value indicated by the evaluation step number signal DSN tothe comparator evaluation voltage setting circuit 5 by outputting anevaluation voltage setting signal DVS.

According to this embodiment, since the lock cancellation signal LCS isgenerated based on the transition of the power supply voltage PSV, it isunnecessary to provide a dedicated terminal for generating the lockcancellation signal LCS. Further, since the reference voltage RV1 isgenerated from the power supply voltage PSV, it is unnecessary toprovide a dedicated power supply for generating the reference voltageRV1. Further, by providing the two comparators 3 and 4, the upper-limitvoltage evaluation and the lower-limit voltage evaluation can besimultaneously performed. As a result, the time required for thecomparisons is reduced.

FIG. 2 is a flowchart showing an operation of the power supply voltagetransition comparison circuit 20A. The power supply voltage transitioncomparison circuit 20A repeats the evaluation step while changing theratio K1 between the power supply voltage PSV and the upper-limitcomparison voltage UCV and the ratio K2 between the power supply voltagePSV and the lower-limit comparison voltage LCV, and thereby determineswhether or not the transition of the power supply voltage PSV matchesthe expected voltage transition. The evaluation step includes generatingan upper-limit comparison voltage UCV and a lower-limit comparisonvoltage LCV from the power supply voltage PSV, comparing the upper-limitcomparison voltage UCV with the reference voltage RV1, comparing thelower-limit comparison voltage LCV with the reference voltage RV1, anddetermining whether or not the power supply voltage PSV matches apredetermined expected voltage based on the comparison results. When thepower supply voltage PSV matches the predetermined expected voltage, thepower supply voltage transition comparison circuit 20A performs the nextevaluation step.

Next, an operation of the power supply voltage transition comparisoncircuit 20A is explained in detail. When the voltage evaluation controlcircuit 9 receives a trigger signal TS indicating the start of a powersupply voltage transition comparison, the process proceeds to a stepS10. The trigger signal TS is, for example, a reset cancellation signalor an instruction from a CPU (Central Processing Unit) (not shown).

(Step S10)

The voltage evaluation control circuit 9 initializes the count value ofthe evaluation step counter 10 to one. Further, the voltage evaluationcontrol circuit 9 outputs an evaluation step number signal DSN to theevaluation voltage setting value output circuit 7 and thereby conveysthe count value of the evaluation step counter 10 to the evaluationvoltage setting value output circuit 7.

(Step S12)

The evaluation voltage setting value output circuit 7 outputs anevaluation voltage setting signal DVS to the comparator evaluationvoltage setting circuit 5 and thereby conveys a setting value group(upper-limit voltage and lower-limit voltage of an expected voltagerange) associated with the count value indicated by the evaluation stepnumber signal DSN to the comparator evaluation voltage setting circuit5. The comparator evaluation voltage setting circuit 5 sets theresistance values of the resistance voltage-dividing circuits 12 and 13based on the evaluation voltage setting signal DVS and thereby sets theratios K1 and K2. As a result, an upper-limit comparison voltage UCV isset so that when the power supply voltage PSV matches the upper-limitvoltage indicated by the evaluation voltage setting signal DVS, theupper-limit comparison voltage UCV matches the reference voltage RV1.Further, a lower-limit comparison voltage LCV is set so that when thepower supply voltage PSV matches the lower-limit voltage indicated bythe evaluation voltage setting signal DVS, the lower-limit comparisonvoltage LCV matches the reference voltage RV1.

(Step S14)

The WAIT counter 11 of the voltage evaluation control circuit 9 measuresan elapsed time from when the evaluation step number signal DSNindicating the count value of the evaluation step counter 10 is outputin the step S10. The WAIT counter 11 measures the elapsed time by, forexample, counting a clock. The voltage evaluation control circuit 9 doesnot output a voltage evaluation implementation instruction signal VDCfor indicating the implementation of a voltage evaluation to the voltageevaluation circuit 8 until the elapsed time reaches a predetermined waittime. By doing so, the voltage evaluation control circuit 9 secures await time for reflecting the upper-limit voltage and the lower-limitvoltage, which are used as setting values, in the comparators 3 and 4.

(Step S20)

The resistance voltage-dividing circuit 12 generates the upper-limitcomparison voltage UCV from the power supply voltage PSV and theresistance voltage-dividing circuit 13 generates the lower-limitcomparison voltage LCV from the power supply voltage PSV. The comparator3 compares the upper-limit comparison voltage UCV with the referencevoltage RV1 and outputs a comparator output signal UCO indicating thecomparison result. The comparator 4 compares the lower-limit comparisonvoltage LCV with the reference voltage RV1 and outputs a comparatoroutput signal LCO indicating the comparison result. Theinverter-equipped AND-gate 6 outputs a logic gate output signal LGObased on the comparator output signals UCO and LCO.

The voltage evaluation control circuit 9 instructs the voltageevaluation circuit 8 to carry out a voltage evaluation by outputting avoltage evaluation implementation instruction signal VDC to the voltageevaluation circuit 8. Upon receiving the voltage evaluationimplementation instruction signal VDC, the voltage evaluation circuit 8evaluates the power supply voltage PSV. When the logic gate outputsignal LGO is at a high level, the voltage evaluation circuit 8determines that the power supply voltage PSV is within the expectedvoltage range and thereby determines that the power supply voltage PSVmatches the expected voltage. When the logic gate output signal LGO isat a low level, the voltage evaluation circuit 8 determines that thepower supply voltage PSV is outside the expected voltage range andthereby determines that the power supply voltage PSV does not match theexpected voltage. When the logic gate output signal LGO is at a highlevel, the voltage evaluation circuit 8 notifies the voltage evaluationcontrol circuit 9 that the voltage evaluation result is “PASS” by usinga voltage evaluation result signal VDR. Further, when the logic gateoutput signal LGO is at a low level, the voltage evaluation circuit 8notifies the voltage evaluation control circuit 9 that the voltageevaluation result is “FAIL” using the voltage evaluation result signalVDR.

(Step S30)

When the voltage evaluation result is “FAIL” in the step S20, theprocess returns to the step S20. When the voltage evaluation result is“PASS” in the step S20, the process proceeds to the step S40.

(Step S40)

When the voltage evaluation result is “PASS”, the voltage evaluationcontrol circuit 9 updates (increments) the count value of the evaluationstep counter 10. In other words, the evaluation step counter 10 countsthe number of evaluation steps based on the result of the evaluation ofthe power supply voltage PSV output from the voltage evaluation circuit8. The voltage evaluation control circuit 9 notifies the evaluationvoltage setting value output circuit 7 of the updated count value byoutputting an evaluation step number signal DSN to the evaluationvoltage setting value output circuit 7.

(Step S42)

The evaluation voltage setting value output circuit 7 changes theevaluation voltage setting signal DVS based on the value of theevaluation step number signal DSN. Specifically, the evaluation voltagesetting value output circuit 7 outputs an evaluation voltage settingsignal DVS indicating setting values (upper-limit voltage andlower-limit voltage of an expected voltage range) associated with theupdated count value indicated by the evaluation step number signal DSN.The comparator evaluation voltage setting circuit 5 changes theresistance values of the resistance voltage-dividing circuits 12 and 13based on the value of the evaluation voltage setting signal DVS.Specifically, the comparator evaluation voltage setting circuit 5 setsthe resistance values of the resistance voltage-dividing circuits 12 and13 based on setting values associated with the updated count value. Inother words, the evaluation voltage setting value output circuit 7 setsthe ratios K1 and K2 based on the setting values associated with theupdated count value.

(Step S50)

The WAIT counter 11 of the voltage evaluation control circuit 9 measuresan elapsed time from when the evaluation step number signal DSNindicating the updated count value of the evaluation step counter 10 isoutput in the step S40. The voltage evaluation control circuit 9 doesnot output the voltage evaluation implementation instruction signal VDCto the voltage evaluation circuit 8 until the elapsed time reaches thepredetermined wait time. By doing so, the voltage evaluation controlcircuit 9 secures a wait time before the next voltage evaluation step.By this wait time, the time for changing the power supply voltage PSVand the setup time for reflecting the upper-limit voltage and thelower-limit voltage corresponding to the updated count value in thecomparators 3 and 4 are secured.

(Steps S60 and S70)

The power supply voltage transition comparison circuit 20A performs avoltage evaluation through an operation similar to that in the step S20(step S60). When the voltage evaluation result is “FAIL” in the stepS60, the process returns to the step S10, whereas when the voltageevaluation result is “PASS” in the step S60, the process proceeds to thestep S80 (step S70).

(Step S80)

The voltage evaluation control circuit 9 determines whether the countvalue of the evaluation step counter 10 is the last value or not basedon an overflow flag of the evaluation step counter 10. When the countvalue of the evaluation step counter 10 is the last value, that is, whenthe count value is equal to the upper limit value for the evaluationstep number, the voltage evaluation control circuit 9 determines thatthe transition of the power supply voltage PSV matches the expectedvoltage transition and hence the process proceeds to a step S90. Whenthe count value of the evaluation step counter 10 is not the last value,the process returns to the step S40.

(Step S90)

The voltage evaluation control circuit 9 outputs a lock cancellationsignal LCS indicating the cancellation of the lock of a circuit to whichaccess is protected (which is described later). In response to the lockcancellation signal LCS, the lock of the circuit to which access isprotected (hereinafter called “access-protected circuit”) is cancelledand the semiconductor integrated circuit in which the access-protectedcircuit is provided is changed to a test mode.

Note that although the evaluation step counter 10 is an up-counter inthe above explanation, a down-counter may be used as the evaluation stepcounter 10.

FIG. 3 is a timing chart showing an operation of the power supplyvoltage transition comparison circuit 20A and a transition of the powersupply voltage PSV. A user possesses information about a plurality ofsetting value groups associated with a plurality of respective voltageevaluation steps and a wait time(s) between the voltage evaluationsteps. Note that each setting value group includes an upper-limitvoltage and a lower-limit voltage of an expected voltage range. A powersupply voltage supply apparatus (not shown) used by the user changes thepower supply voltage PSV as shown in FIG. 3. The power supply voltagesupply apparatus controls the voltage level of the power supply voltagePSV based on the plurality of setting value groups and controls thetransition timing of the power supply voltage PSV based on the timing ofa trigger signal TS and the wait time between voltage evaluation steps.In the example shown in FIG. 3, the number of voltage evaluation stepsis three. The three voltage evaluation steps correspond to the steps 1to 3.

In a section T1, the power supply voltage transition comparison circuit20A performs the operations in the steps S10, S12 and S14. The powersupply voltage transition comparison circuit 20A initializes the countvalue of the evaluation step counter 10 to one in response to thetrigger signal TS, and sets the resistance values of the resistancevoltage-dividing circuits 12 and 13 based on the upper-limit voltage andthe lower-limit voltage for the step 1, which is the first step. In thisexample, the upper-limit voltage and the lower-limit voltage for thestep 1 are 5.0V and 4.0V, respectively. Meanwhile, the power supplyvoltage supply apparatus changes the power supply voltage PSV from thenormal voltage 5.0V to a voltage between the upper-limit voltage and thelower-limit voltage for the step 1 (for example, 4.5V) in response tothe trigger signal TS. Note that the illustration of the wait time inthe step S14 is omitted in the figure.

In a section T2, the power supply voltage transition comparison circuit20A performs the operations in the steps S20 and S30. The power supplyvoltage transition comparison circuit 20A performs a voltage evaluationof the step 1 and determines, that the power supply voltage PSV isbetween the upper-limit voltage 5.0V and the lower-limit voltage 4.0V.Meanwhile, the power supply voltage supply apparatus keeps the powersupply voltage PSV between the upper-limit voltage and the lower-limitvoltage for the step 1.

In a section T3, the power supply voltage transition comparison circuit20A performs the operations in the steps S40, S42 and S50. The voltageevaluation control circuit 9 increments the count value of theevaluation step counter 10 to two. The comparator evaluation voltagesetting circuit 5 changes the resistance values of the resistancevoltage-dividing circuits 12 and 13 and sets them to resistance valuescorresponding to the upper-limit voltage and the lower-limit voltage forthe step 2. The upper-limit voltage and the lower-limit voltage for thestep 2 are 3.0V and 2.0V, respectively. Meanwhile, the power supplyvoltage supply apparatus changes the power supply voltage PSV from thevoltage between the upper-limit voltage and the lower-limit voltage forthe step 1 to a voltage between the upper-limit voltage and thelower-limit voltage for the step 2 (for example, 2.5V). The wait time inthe step S50 secures the time for changing the power supply voltage PSVand the setup time for reflecting the upper-limit voltage and thelower-limit voltage for the step 2 in the comparators 3 and 4.

In a section T4, the power supply voltage transition comparison circuit20A performs the operations in the steps S60 and S70. The power supplyvoltage transition comparison circuit 20A performs a voltage evaluationof the step 2 and determines that the power supply voltage PSV isbetween the upper-limit voltage 3.0V and the lower-limit voltage 2.0V.Meanwhile, the power supply voltage supply apparatus keeps the powersupply voltage PSV between the upper-limit voltage and the lower-limitvoltage for the step 2.

In a section T5, the power supply voltage transition comparison circuit20A performs the operations in the steps S40, S42 and S50. The voltageevaluation control circuit 9 increments the count value of theevaluation step counter 10 to three. The comparator evaluation voltagesetting circuit 5 changes the resistance values of the resistancevoltage-dividing circuits 12 and 13 and sets them to resistance valuescorresponding to the upper-limit voltage and the lower-limit voltage forthe step 3. The upper-limit voltage and the lower-limit voltage for thestep 3 are 4.0V and 3.0V, respectively. Meanwhile, the power supplyvoltage supply apparatus changes the power supply voltage PSV from thevoltage between the upper-limit voltage and the lower-limit voltage forthe step 2 to a voltage between the upper-limit voltage and thelower-limit voltage for the step 3 (for example, 3.5V). The wait time inthe step S50 secures the time for changing the power supply voltage PSVand the setup time for reflecting the upper-limit voltage and thelower-limit voltage for the step 3 in the comparators 3 and 4.

In a section T6, the power supply voltage transition comparison circuit20A performs the operations in the steps S60, S70, S80 and S90. Thepower supply voltage transition comparison circuit 20A performs avoltage evaluation of the step 3 and determines that the power supplyvoltage PSV is between the upper-limit voltage 4.0V and the lower-limitvoltage 3.0V. Since the step 3 is the last step, the voltage evaluationcontrol circuit 9 outputs a lock cancellation signal LCS. Meanwhile, thepower supply voltage supply apparatus keeps the power supply voltage PSVbetween the upper-limit voltage and the lower-limit voltage for the step3.

In a section T7, the power supply voltage supply apparatus returns thepower supply voltage PSV to the normal voltage 5.0V.

Note that the control method for the power supply voltage transitioncomparison circuit 20A performed by the voltage evaluation controlcircuit 9 may be implemented by a computer that runs based on a computerprogram. The control method includes outputting an evaluation stepnumber signal DSN indicating a count value to the evaluation voltagesetting value output circuit 7, outputting a voltage evaluationimplementation instruction signal VDC to the voltage evaluation circuit8, and updating the count value based on a voltage evaluation resultsignal VDR.

Note that the comparator evaluation voltage setting circuit 5 generatesthe upper-limit comparison voltage UCV and the lower-limit comparisonvoltage LCV as divided voltages of the power supply voltage PSV. Thecomparator 3 compares the upper-limit comparison voltage UCV with thereference voltage RV1. The comparator 4 compares the lower-limitcomparison voltage LCV with the reference voltage RV1. When the voltageevaluation circuit 8 receives the voltage evaluation implementationinstruction signal VDC, the voltage evaluation circuit 8 evaluates thepower supply voltage PSV based on the comparator output signals UCO andLCO output by the comparators 3 and 4 and outputs a voltage evaluationresult signal VDR indicating the evaluation result. The evaluationvoltage setting value output circuit 7 sets a ratio K1 between the powersupply voltage PSV and the upper-limit comparison voltage UCV and aratio K2 between the power supply voltage PSV and the lower-limitcomparison voltage LCV based on a predetermined setting value(s)associated with the value of the evaluation step number signal DSN.

The control method may include securing a predetermined wait time fromwhen the evaluation step number signal DSN is output to when the voltageevaluation implementation instruction signal VDC is output. The controlmethod may include outputting a lock cancellation signal LCS indicatingthe cancellation of the lock of an access-protected circuit when thecount value is the last value and the voltage evaluation result signalVDR indicates that the power supply voltage PSV is within apredetermined expected voltage range.

Modified Example of First Embodiment

Next, a modified example of the first embodiment is explained. Referringto FIG. 4, a power supply voltage transition comparison circuit 20Aaccording to this modified example includes a voltage evaluation circuit8A in place of the voltage evaluation circuit 8. The operation of thevoltage evaluation circuit 8A in the step S20 is different from that ofthe voltage evaluation circuit 8 in the step S20. The operation of thevoltage evaluation circuit 8A in the step S60 is the same as that of thevoltage evaluation circuit 8 in the step S60. Further, the step S30 inthis modified example is different from that in the first embodiment.

An operation of the voltage evaluation circuit 8A performed in the stepS20 is explained. When the voltage evaluation circuit 8A receives avoltage evaluation implementation instruction signal VDC, the voltageevaluation circuit 8A evaluates the power supply voltage PSV. When thelogic gate output signal LGO is at a high level, the voltage evaluationcircuit 8A notifies the voltage evaluation control circuit 9 that thevoltage evaluation result is “PASS” by using a voltage evaluation resultsignal VDR. When the logic gate output signal LGO is at a low level, thevoltage evaluation circuit 8A performs a voltage evaluation in eachcycle of the operation clock and thereby repeatedly performs the voltageevaluation. If the logic gate output signal LGO does not become a highlevel even after repeating the voltage evaluation a predetermined numberof times, the voltage evaluation circuit 8A notifies the voltageevaluation control circuit 9 that the voltage evaluation result is“FAIL” by using a voltage evaluation result signal VDR.

The power supply voltage transition comparison circuit 20A is explainedin a more detailed manner. The voltage evaluation circuit 8A acquiresthe count value of the evaluation step counter 10 through the evaluationstep number signal DSN. When the voltage evaluation circuit 8A receivesa voltage evaluation implementation instruction signal VDC when theevaluation step counter 10 has the initial value, the voltage evaluationcircuit 8A repeats the voltage evaluation until the voltage evaluationcircuit 8A detects a high-level logic gate output signal LGO or thenumber of voltage evaluations reaches a predetermined number.

The voltage evaluation circuit 8A includes a down-counter 17 that countsthe number of voltage evaluations in a descending manner. The voltageevaluation circuit 8A repeats the voltage evaluation until the countvalue of the down-counter 17 becomes zero. When the voltage evaluationcircuit 8A receives a voltage evaluation implementation instructionsignal VDC, the voltage evaluation circuit 8A initializes thedown-counter 17. For example, when the voltage evaluation is to berepeated ten times, the down-counter 17 is initialized to ten.Alternatively, a CPU (not shown) may set an arbitrary value in thedown-counter 17 before the voltage evaluation is started.

When the voltage evaluation control circuit 9 receives a voltageevaluation result signal VDR indicating that the voltage evaluationresult is “FAIL” when the evaluation step counter 10 has the initialvalue (FAIL at step S30), the process returns to the start (triggersignal TS waiting state) in FIG. 2. Note that the number of voltageevaluations may be counted by using an up-counter instead of thedown-counter 17. The number of voltage evaluations performed by thevoltage evaluation circuit 8A in the step S20 does not necessarily haveto be restricted to any particular number.

Second Embodiment

FIG. 5 is a circuit configuration diagram of a power supply voltagetransition comparison circuit 20B according to a second embodiment. Thepower supply voltage transition comparison circuit 20B is different fromthe power supply voltage transition comparison circuit 20A in that thepower supply voltage transition comparison circuit 20B includes atransition number WAIT time setting circuit 14 and an expected voltagesetting circuit 15 as additional components. Further, the power supplyvoltage transition comparison circuit 20B includes an evaluation voltagesetting value output circuit 7B in place of the evaluation voltagesetting value output circuit 7 of the power supply voltage transitioncomparison circuit 20A and includes a voltage evaluation control circuit9B in place of the voltage evaluation control circuit 9 of the circuit20A. The voltage evaluation control circuit 9B includes an evaluationstep counter 10 and a WAIT counter 11B. The transition number WAIT timesetting circuit 14 outputs a transition number WAIT time setting signalTWS to the voltage evaluation control circuit 9B based on the evaluationstep number signal DSN. The expected voltage setting circuit 15 outputsan expected voltage setting signal EVS to the evaluation voltage settingvalue output circuit 7B based on the evaluation step number signal DSN.

FIG. 6 is a table held by the transition number WAIT time settingcircuit 14. The transition number WAIT time setting circuit 14 holdsWAIT count value-s which are associated with values for the evaluationstep number signal DSN. The transition number WAIT time setting circuit14 can change the held WAIT count values. The transition number WAITtime setting circuit 14 needs to hold at least the evaluation stepnumber (voltage transition number) and the WAIT time. For example, thetransition number WAIT time setting circuit 14 can store the WAIT countvalues in a non-volatile memory. The WAIT count values are settingvalues for the expected voltage transition.

FIG. 7 is a table held by the expected voltage setting circuit 15. Theexpected voltage setting circuit 15 holds values for the upper-limitvoltage and the lower-limit voltage which are associated with values forthe evaluation step number signal DSN. The expected voltage settingcircuit 15 can change the values for the upper-limit voltage andlower-limit voltage held therein. The expected voltage setting circuit15 needs to hold at least the expected voltage range. For example, theexpected voltage setting circuit 15 can store the values for theupper-limit voltage and lower-limit voltage in a non-volatile memory.The values for the upper-limit voltage and lower-limit voltage aresetting values for the expected voltage transition.

FIGS. 6 and 7 show example structures for tables for a case where thenumber of evaluation steps (number of voltage transitions) can bearbitrarily set in a range from 1 to 7. The values in the tables inFIGS. 6 and 7 are example values for a case where the number ofevaluation steps (number of voltage transitions) is three.

A user sets the number of evaluation steps and a WAIT time(s) betweenevaluation steps in the transition number WAIT time setting circuit 14and sets an expected voltage range for each evaluation step in theexpected voltage setting circuit 15 before starting the power supplyvoltage transition comparison. Specifically, when the number ofevaluation steps is set to three, the user sets, for the transitionnumber WAIT time setting circuit 14, values greater than zero as WAITcount values corresponding to the values 1 to 3 for the evaluation stepnumber signal DSN, and sets zero as WAIT count values corresponding tothe values 4 to 7 for the evaluation step number signal DSN. The WAITcount value that is greater than zero corresponds to the length of theWAIT time. The user sets values of the upper-limit voltage and thelower-limit voltage corresponding to the values of the evaluation stepnumber signal DSN.

Next, an operation of the power supply voltage transition comparisoncircuit 20B is explained with reference to FIG. 8. When the voltageevaluation control circuit 9B receives a trigger signal TS indicatingthe start of a power supply voltage transition comparison, the processproceeds to a step S10.

(Step S10).

The voltage evaluation control circuit 9B initializes the count value ofthe evaluation step counter 10 to one, and outputs an evaluation stepnumber signal DSN to the evaluation voltage setting value output circuit7B, the transition number WAIT time setting circuit 14, and the expectedvoltage setting circuit 15 and thereby conveys the count value of theevaluation step counter 10 to them. The transition number WAIT timesetting circuit 14 outputs a transition number WAIT time setting signalTWS to the voltage evaluation control circuit 9B and thereby conveys aWAIT count value corresponding to the value of the evaluation stepnumber signal DSN to the voltage evaluation control circuit 9B. Theexpected voltage setting circuit 15 outputs an expected voltage settingsignal EVS to the evaluation voltage setting value output circuit 7B andthereby conveys the values of the upper-limit voltage and thelower-limit voltage corresponding to the value of the evaluation stepnumber signal DSN to the evaluation voltage setting value output circuit7B.

(Step S12)

The evaluation voltage setting value output circuit 7B outputs anevaluation voltage setting signal DVS to the comparator evaluationvoltage setting circuit 5 and thereby conveys the upper-limit voltageand the lower-limit voltage corresponding to the value of the evaluationstep number signal DSN to the comparator evaluation voltage settingcircuit 5. The comparator evaluation voltage setting circuit 5 sets theresistance values of the resistance voltage-dividing circuits 12 and 13based on the evaluation voltage setting signal DVS and thereby sets theratios K1 and K2.

(Step S14)

The WAIT counter 11B of the voltage evaluation control circuit 9B countsa clock up to the WAIT count value conveyed from the transition numberWAIT time setting circuit 14 in the step S10, and thereby secures a waittime. The voltage evaluation control circuit 9B does not output thevoltage evaluation implementation instruction signal VDC for indicatingthe implementation of a voltage evaluation to the voltage evaluationcircuit 8 until the wait time has elapsed.

(Steps S20 and S30)

The step S20 according to this embodiment is the same as the step S20according to the first embodiment. However, the voltage evaluationcontrol circuit 9 of the first embodiment is replaced in this embodimentby the voltage evaluation control circuit 9B. The step S30 according tothis embodiment is the same as the step S30 according to the firstembodiment.

(Step S40)

When the voltage evaluation result is “PASS”, the voltage evaluationcontrol circuit 9B updates (increments) the count value of theevaluation step counter 10. The voltage evaluation control circuit 9Boutputs an evaluation step number signal DSN to the evaluation voltagesetting value output circuit 7B, the transition number WAIT time settingcircuit 14, and the expected voltage setting circuit 15, and therebyconveys the count value of the evaluation step counter 10 to them. Thetransition number WAIT time setting circuit 14 outputs a transitionnumber WAIT time setting signal TWS to the voltage evaluation controlcircuit 9B and thereby conveys a WAIT count value corresponding to thevalue of the evaluation step number signal DSN to the voltage evaluationcontrol circuit 9B. The expected voltage setting circuit 15 outputs anexpected voltage setting signal EVS to the evaluation voltage settingvalue output circuit 7B and thereby conveys the values of theupper-limit voltage and the lower-limit voltage corresponding to thevalue of the evaluation step number signal DSN to the evaluation voltagesetting value output circuit 7B.

(Step S42)

The evaluation voltage setting value output circuit 7B changes theevaluation voltage setting signal DVS based on the values of theupper-limit voltage and the lower-limit voltage conveyed from theexpected voltage setting circuit 15 in the step S40. Specifically, theevaluation voltage setting value output circuit 7B outputs an evaluationvoltage setting signal DVS indicating the values of the upper-limitvoltage and the lower-limit voltage conveyed from the expected voltagesetting circuit 15 in the step S40. The comparator evaluation voltagesetting circuit 5 changes the resistance values of the resistancevoltage-dividing circuits 12 and 13 based on the evaluation voltagesetting signal DVS and thereby changes the ratios K1 and K2.

(Step S44)

When the WAIT count value conveyed from the transition number WAIT timesetting circuit 14 to the voltage evaluation control circuit 9B in thestep S40 is greater than zero, the process proceeds to a step S50. Whenthe WAIT count value conveyed from the transition number WAIT timesetting circuit 14 to the voltage evaluation control circuit 9B in thestep S40 is zero, the voltage evaluation control circuit 9B determinesthat the transition of the power supply voltage PSV matches the expectedvoltage transition and hence the process proceeds to a step S90.

(Step S50)

The WAIT counter 11B of the voltage evaluation control circuit 9B countsa clock up to the WAIT count value conveyed from the transition numberWAIT time setting circuit 14 in the step S40, and thereby secures a waittime. The voltage evaluation control circuit 9B does not output thevoltage evaluation implementation instruction signal VDC for indicatingthe implementation of a voltage evaluation to the voltage evaluationcircuit 8 until the wait time has elapsed.

(Steps S60 and S70)

The power supply voltage transition comparison circuit 20B performs avoltage evaluation through an operation similar to that in the step S20(step S60). When the voltage evaluation result is “FAIL” in the stepS60, the process returns to the step S10, whereas when the voltageevaluation result is “PASS” in the step S60, the process returns to thestep S40 (step S70).

(Step S90)

The voltage evaluation control circuit 9B outputs a lock cancellationsignal LCS indicating the cancellation of the lock of anaccess-protected circuit.

According to this embodiment, the voltage evaluation control circuit 9Bdetermines the timing at which the voltage evaluation circuit 8evaluates the power supply voltage PSV based on the WAIT count valuethat is held and can be changed by the transition number WAIT timesetting circuit 14. As a result, the user can change and arbitrarily setthe wait time between evaluation steps.

According to this embodiment, the voltage evaluation control circuit 9Bdetermines the number of times that the evaluation voltage setting valueoutput circuit 7B changes the ratio K1 between the power supply voltagePSV and the upper-limit comparison voltage UCV and the ratio K2 betweenthe power supply voltage PSV and the lower-limit comparison voltage LCVbased on the WAIT count value that is held and can be changed by thetransition number WAIT time setting circuit 14. As a result, the usercan change and arbitrarily set the number of times that the evaluationstep is repeated.

According to this embodiment, the evaluation voltage setting valueoutput circuit 7B sets the ratio K1 between the power supply voltage PSVand the upper-limit comparison voltage UCV and the ratio K2 between thepower supply voltage PSV and the lower-limit comparison voltage LCVbased on the values of the upper-limit voltage and the lower-limitvoltage that are held and can be changed by the expected voltage settingcircuit 15. As a result, the user can change and arbitrarily set theexpected voltage in each evaluation step.

As described above, it is possible to change and arbitrarily set theexpected voltage transition in the power supply voltage transitioncomparison circuit 20B. Therefore, it is possible to set a differentexpected voltage transition for each individual semiconductor producteven when they are the same type of semiconductor product. As a result,a user can conceal the expected voltage transition of his/hersemiconductor product from other users who use the same type ofsemiconductor product as that of his/her semiconductor product.Therefore, it is possible to prevent an outsider from illegitimatelygenerating the lock cancellation signal LCS.

Third Embodiment

FIG. 9 is a circuit configuration diagram of a power supply voltagetransition comparison circuit 20C according to a third embodiment. Theconfiguration of the power supply voltage transition comparison circuit20C is different from that of the power supply voltage transitioncomparison circuit 20B in the following points. The power supply voltagetransition comparison circuit 20C includes a comparator 3C in place ofthe comparators 3 and 4 of the power supply voltage transitioncomparison circuit 20B, includes a comparator evaluation voltage settingcircuit 5C in place of the comparator evaluation voltage setting circuit5 of the circuit 20B, and does not include the inverter-equippedAND-gate 6 of the circuit 20B. Further, the power supply voltagetransition comparison circuit 20C includes an evaluation voltage settingvalue output circuit 7C in place of the evaluation voltage setting valueoutput circuit 7B of the circuit 20B, and includes a voltage evaluationcircuit 8C in place of the voltage evaluation circuit 8 of the circuit20B. The BGR circuit 2 outputs the reference voltage RV1 to the +inputterminal of the comparator 3C.

The comparator evaluation voltage setting circuit 5C includes aresistance voltage-dividing circuit 12C. The resistance voltage-dividingcircuit 12C generates a comparison voltage CV from the power supplyvoltage PSV and outputs the generated comparison voltage CV to the−input terminal of the comparator 3C. The comparison voltage CV is adivided voltage of the power supply voltage PSV.

The comparator evaluation voltage setting circuit 5C sets a ratio Kbetween the power supply voltage PSV and the comparison voltage CV basedon the evaluation voltage setting signal DVS. Note that the evaluationvoltage setting signal DVS indicates the upper-limit voltage or thelower-limit voltage of the expected voltage range depending on thesituation. When the evaluation voltage setting signal DVS indicates theupper-limit voltage, the comparator evaluation voltage setting circuit5C sets the ratio K by setting the resistance value of the resistancevoltage-dividing circuit 12C so that when the power supply voltage PSVmatches the upper-limit voltage, the comparison voltage CV matches thereference voltage RV1. When the evaluation voltage setting signal DVSindicates the lower-limit voltage, the comparator evaluation voltagesetting circuit 5C sets the ratio K by setting the resistance value ofthe resistance voltage-dividing circuit 12C so that when the powersupply voltage PSV matches the lower-limit voltage, the comparisonvoltage CV matches the reference voltage RV1. When the value indicatedby the evaluation voltage setting signal DVS changes, the comparatorevaluation voltage setting circuit 5C changes the ratio K so that theratio K conforms to the new value.

The comparator 3C performs a voltage upper-limit comparison or a voltagelower-limit comparison depending on the situation. The comparator 3Ccompares the reference voltage RV1 input to the +input terminal with thecomparison voltage CV input to the −input terminal and outputs acomparator output signal CO, which is a digital signal indicating thecomparison result, to the voltage evaluation circuit 8C. The comparatoroutput signal CO is at a low level when the comparison voltage CV islower than the reference voltage RV1. Further, the comparator outputsignal CO is at a high level when the comparison voltage CV is higherthan the reference voltage RV1. In other words, when the power supplyvoltage PSV is lower than the voltage indicated by the evaluationvoltage setting signal DVS, the comparator output signal CO is at a lowlevel, whereas when the power supply voltage PSV is higher than thevoltage indicated by the evaluation voltage setting signal DVS, thecomparator output signal CO is at a high level.

The voltage evaluation circuit 8C includes a WAIT counter 18. Thevoltage evaluation circuit 8C outputs an upper/lower selector signal ULSto the evaluation voltage setting value output circuit 7C. Theupper/lower selector signal ULS has a value indicating an upper-limitvoltage setting mode (e.g., high level) or a value indicating alower-limit voltage setting mode (e.g., low level). When the voltageevaluation circuit 8C receives a voltage evaluation implementationinstruction signal VDC from the voltage evaluation control circuit 9B,the voltage evaluation circuit 8C determines whether or not the powersupply voltage PSV is within the expected voltage range and outputs avoltage evaluation result signal VDR indicating the evaluation result tothe voltage evaluation control circuit 9B.

When the upper/lower selector signal ULS has a value indicating theupper-limit voltage setting mode, the voltage evaluation circuit 8Cdetermines whether or not the power supply voltage PSV is lower than theupper-limit voltage of the expected voltage range based on thecomparator output signal CO. When the upper/lower selector signal ULShas a value indicating the lower-limit voltage setting mode, the voltageevaluation circuit 8C determines whether or not the power supply voltagePSV is higher than the lower-limit voltage of the expected voltage rangebased on the comparator output signal CO. In the cases when the powersupply voltage PSV is lower than the upper-limit voltage and higher thanthe lower-limit voltage, the voltage evaluation circuit 8C determinesthat the power supply voltage PSV is within the expected voltage range.In the other cases, the voltage evaluation circuit 8C determines thatthe power supply voltage PSV is not within the expected voltage range.The voltage evaluation circuit 8C secures a predetermined wait time byusing the WAIT counter 18 after changing the upper/lower selector signalULS, and then evaluates the power supply voltage PSV based on thecomparator output signal CO.

The configurations and the operations of the voltage evaluation controlcircuit 9B, the transition number WAIT time setting circuit 14, and theexpected voltage setting circuit 15 of this embodiment are the same asthose in the second embodiment.

When the upper/lower selector signal ULS has a value indicating theupper-limit voltage setting mode, the evaluation voltage setting valueoutput circuit 7C outputs an evaluation voltage setting signal DVS andthereby notifies the comparator evaluation voltage setting circuit 5C ofthe upper-limit voltage corresponding to the value of the evaluationstep number signal DSN. When the upper/lower selector signal ULS has avalue indicating the lower-limit voltage setting mode, the evaluationvoltage setting value output circuit 7C outputs an evaluation voltagesetting signal DVS and thereby notifies the comparator evaluationvoltage setting circuit 5C of the lower-limit voltage corresponding tothe value of the evaluation step number signal DSN. Note that theupper-limit voltage and the lower-limit voltage are the upper-limitvoltage and the lower-limit voltage conveyed from the expected voltagesetting circuit 15 through the expected voltage setting signal EVS.

Therefore, the evaluation voltage setting value output circuit 7Cchanges the voltage setting mode between the upper-limit voltage settingmode and the lower-limit voltage setting mode based on the upper/lowerselector signal ULS. In the upper-limit voltage setting mode, theevaluation voltage setting value output circuit 7C sets the ratio Kbetween the power supply voltage PSV and the comparison voltage CV basedon the upper-limit voltage of the expected voltage range. In thelower-limit voltage setting mode, the evaluation voltage setting valueoutput circuit 7C sets the ratio K between the power supply voltage PSVand the comparison voltage CV based on the lower-limit voltage of theexpected voltage range.

FIG. 10 is a flowchart showing an operation of the voltage evaluationcircuit 8C. An operation of the voltage evaluation circuit 8C isexplained with reference to FIG. 10.

(Step S100)

The voltage evaluation circuit 8C waits for an input of a voltageevaluation implementation instruction signal VDC. When the voltageevaluation circuit 8C receives the voltage evaluation implementationinstruction signal VDC, the process proceeds to the step S102.

(Step S102)

The voltage evaluation circuit 8C changes the level of the upper/lowerselector signal ULS from the low level to a high level. The low levelindicates the lower-limit voltage setting mode and the high levelindicates the upper-limit voltage setting mode.

(Step S104)

The WAIT counter 18 of the voltage evaluation circuit 8C measures anelapsed time from when the upper/lower selector signal ULS is changed inthe step S102. For example, the WAIT counter 18 measures the elapsedtime by counting a clock. The voltage evaluation circuit 8C does notdetermine whether or not the power supply voltage PSV is lower than theupper-limit voltage based on the comparator output signal CO until theelapsed time reaches a predetermined wait time. In this manner, thevoltage evaluation circuit 8C secures a wait time for reflecting theupper-limit voltage, which is used as a setting value, in the comparator3C.

(Step S106)

The voltage evaluation circuit 8C determines whether or not the powersupply voltage PSV is lower than the upper-limit voltage based on thecomparator output signal CO. The voltage evaluation circuit 8Cdetermines that the power supply voltage PSV is lower than theupper-limit voltage when the comparator output signal CO is at a lowlevel. Note that since the voltage evaluation circuit 8C is the circuitthat changes the upper/lower selector signal ULS, the voltage evaluationcircuit 8C recognizes which of the upper-limit voltage comparison andthe lower-limit voltage comparison the comparator 3C is performing.

(Steps S108, S110 and S112)

The voltage evaluation circuit 8C changes the level of the upper/lowerselector signal ULS from the high level to a low level (step S108). TheWAIT counter 18 of the voltage evaluation circuit 8C measures an elapsedtime from when the upper/lower selector signal ULS is changed in thestep S108. The voltage evaluation circuit 8C does not determine whetheror not the power supply voltage PSV is higher than the lower-limitvoltage based on the comparator output signal CO until the elapsed timereaches a predetermined wait time. In this manner, the voltageevaluation circuit 8C secures a wait time for reflecting the lower-limitvoltage, which is used as a setting value, in the comparator 3C (stepS110). The voltage evaluation circuit 8C determines whether or not thepower supply voltage PSV is higher than the lower-limit voltage based onthe comparator output signal CO (step S112). The voltage evaluationcircuit 8C determines that the power supply voltage PSV is higher thanthe lower-limit voltage when the comparator output signal CO is at ahigh level.

(Step S114)

In the cases when the power supply voltage PSV is lower than theupper-limit voltage in the step S106 and is higher than the lower-limitvoltage in the step S112, the voltage evaluation circuit 8C determinesthat the power supply voltage PSV is within the expected voltage range.In the other cases, the voltage evaluation circuit 8C determines thatthe power supply voltage PSV is not within the expected voltage range.When the voltage evaluation circuit 8C determines that the power supplyvoltage PSV is within the expected voltage range, the voltage evaluationcircuit 8C notifies the voltage evaluation control circuit 9B that thevoltage evaluation result is “PASS” by using a voltage evaluation resultsignal VDR. Further, when the voltage evaluation circuit 8C determinesthat the power supply voltage PSV is not within the expected voltagerange, the voltage evaluation circuit 8C notifies the voltage evaluationcontrol circuit 9B that the voltage evaluation result is “FAIL” using avoltage evaluation result signal VDR.

FIG. 11 is a timing chart showing an operation of the power supplyvoltage transition comparison circuit 20C and a transition of the powersupply voltage PSV. A user possesses information about a plurality ofsetting value groups associated with a plurality of respective voltageevaluation steps, a wait time(s) between the voltage evaluation steps(wait time(s) in steps S14 and S50), and a wait time(s) within thevoltage evaluation steps (wait time(s) in steps S104 and S110). Notethat each setting value group includes the upper-limit voltage and thelower-limit voltage of an expected voltage range. A power supply voltagesupply apparatus (not shown) used by the user changes the power supplyvoltage PSV as shown in FIG. 11. The power supply voltage supplyapparatus controls the voltage level of the power supply voltage PSVbased on the plurality of setting value groups and controls thetransition timing of the power supply voltage PSV based on the timing ofa trigger signal TS, the wait time(s) between the voltage evaluationsteps, and the wait time(s) within the voltage evaluation steps.

In the example shown in FIG. 11, the number of voltage evaluation stepsis three. The three voltage evaluation steps correspond to the steps 1to 3. The step 1 includes an upper-limit voltage evaluation step 1-1 anda lower-limit voltage evaluation step 1-2. The step 2 includes anupper-limit voltage evaluation step 2-1 and a lower-limit voltageevaluation step 2-2. The step 3 includes an upper-limit voltageevaluation step 3-1 and a lower-limit voltage evaluation step 3-2.

In a section T1, when the voltage evaluation control circuit 9B receivesa trigger signal TS indicating the start of a power supply voltagetransition comparison, the voltage evaluation control circuit 9Binitializes the count value of the evaluation step counter 10 to one,and outputs an evaluation step number signal DSN to the evaluationvoltage setting value output circuit 7C, the transition number WAIT timesetting circuit 14, and the expected voltage setting circuit 15 andthereby conveys the count value of the evaluation step counter 10 (=1)to them. The transition number WAIT time setting circuit 14 outputs atransition number WAIT time setting signal TWS to the voltage evaluationcontrol circuit 9R and thereby conveys a WAIT count value (=3)corresponding to the value of the evaluation step number signal DSN (=1)to the voltage evaluation control circuit 9B. The expected voltagesetting circuit 15 outputs an expected voltage setting signal EVS to theevaluation voltage setting value output circuit 7C and thereby conveysthe values of the upper-limit voltage and the lower-limit voltage (=5.0Vand 4.0V) corresponding to the value of the evaluation step numbersignal DSN (=1) to the evaluation voltage setting value output circuit7C. The WAIT counter 11B of the voltage evaluation control circuit 9Bcounts a clock up to the WAIT count value (=3) conveyed from thetransition number WAIT time setting circuit 14 and thereby secures await time. Meanwhile, the power supply voltage supply apparatus changesthe power supply voltage PSV from the normal voltage 5.0V to a voltagebetween the upper-limit voltage and the lower-limit voltage for the step1 (for example, 4.5V) in response to the trigger signal TS.

In a section T2-1, the power supply voltage transition comparisoncircuit 20C performs the upper-limit voltage evaluation step 1-1.Specifically, the voltage evaluation control circuit 9B instructs thevoltage evaluation circuit 8C to carry out a voltage evaluation byoutputting a voltage evaluation implementation instruction signal VDC tothe voltage evaluation circuit 8C. Upon receiving the voltage evaluationimplementation instruction signal VDC (Yes at step S100), the voltageevaluation circuit 8C changes the level of the upper/lower selectorsignal ULS from the low level to a high level (step S102). Since theupper/lower selector signal ULS is at the high level, the evaluationvoltage setting value output circuit 7C outputs an evaluation voltagesetting signal DVS to the comparator evaluation voltage setting circuit5C and thereby conveys the upper-limit voltage (=5.017) corresponding tothe value of the evaluation step number signal DSN (=1) to thecomparator evaluation voltage setting circuit 5C. The comparatorevaluation voltage setting circuit 5C sets the resistance value of theresistance voltage-dividing circuit 12C based on the evaluation voltagesetting signal DVS and thereby sets the ratio K. The resistancevoltage-dividing circuit 12C generates a comparison voltage CV from thepower supply voltage PSV. The comparator 3C compares the comparisonvoltage CV with the reference voltage RV1 and outputs a comparatoroutput signal CO indicating the comparison result. The voltageevaluation circuit 8C secures a wait time (step S104), and thendetermines that the power supply voltage PSV is lower than theupper-limit voltage 5.0V based on the comparator output signal CO (stepS106).

In a section T2-2, the power supply voltage transition comparisoncircuit 20C performs the lower-limit voltage evaluation step 1-2.Specifically, the voltage evaluation circuit 8C changes the level of theupper/lower selector signal ULS from the high level to a low level (stepS108). Since the upper/lower selector signal ULS is at the low level,the evaluation voltage setting value output circuit 7C outputs anevaluation voltage setting signal DVS to the comparator evaluationvoltage setting circuit 5C and thereby conveys the lower-limit voltage(=4.0V) corresponding to the value of the evaluation step number signalDSN (=1) to the comparator evaluation voltage setting circuit 5C. Thecomparator evaluation voltage setting circuit 5C sets the resistancevalue of the resistance voltage-dividing circuit 12C based on theevaluation voltage setting signal DVS and thereby sets the ratio K. Theresistance voltage-dividing circuit 12C generates a comparison voltageCV from the power supply voltage PSV. The comparator 3C compares thecomparison voltage CV with the reference voltage RV1 and outputs acomparator output signal CO indicating the comparison result. Thevoltage evaluation circuit 8C secures a wait time (step S110), and thendetermines that the power supply voltage PSV is higher than thelower-limit voltage 4.0V based on the comparator output signal CO (stepS112).

Since the power supply voltage PSV is lower than the upper-limit voltage5.0V and higher than the lower-limit voltage 4.0V, the voltageevaluation circuit 8C determines that the power supply voltage PSV iswithin the expected voltage range and notifies the voltage evaluationcontrol circuit 9B that the voltage evaluation result is “PASS”, byusing a voltage evaluation result signal VDR (step S114). Meanwhile, thepower supply voltage supply apparatus keeps the power supply voltage PSVbetween the upper-limit voltage and the lower-limit voltage for the step1 in the sections T2-1 and T2-2.

In a section T3, the voltage evaluation control circuit 9B incrementsthe count value of the evaluation step counter 10 to two, and outputs anevaluation step number signal DSN to the evaluation voltage settingvalue output circuit 7C, the transition number WAIT time setting circuit14, and the expected voltage setting circuit 15 and thereby conveys thecount value of the evaluation step counter 10 (=2) to them. Thetransition number WAIT time setting circuit 14 outputs a transitionnumber WAIT time setting signal TWS to the voltage evaluation controlcircuit 9B and thereby conveys a WAIT′ count value (=10) correspondingto the value of the evaluation step number signal DSN (=2) to thevoltage evaluation control circuit 9B. The expected voltage settingcircuit 15 outputs an expected voltage setting signal EVS to theevaluation voltage setting value output circuit 7C and thereby conveysthe values of the upper-limit voltage and the lower-limit voltage (=3.0Vand 2.0V) corresponding to the value of the evaluation step numbersignal DSN (=2) to the evaluation voltage setting value output circuit7C. The WAIT counter 11B of the voltage evaluation control circuit 9Bcounts a clock up to the WAIT count value (=10) conveyed from thetransition number WAIT time setting circuit 14 and thereby secure-s await time. Meanwhile, the power supply voltage supply apparatus changesthe power supply voltage PSV from the voltage between the upper-limitvoltage and the lower-limit voltage for the step 1 to a voltage betweenthe upper-limit voltage and the lower-limit voltage for the step 2 (forexample, 2.5V).

In a section T4-1, the power supply voltage transition comparisoncircuit 20C performs the upper-limit voltage evaluation step 2-1. Theoperation of the power supply voltage transition comparison circuit 20Cperformed in the section T4-1 is similar to that of the power supplyvoltage transition comparison circuit 20C performed in the section T2-1.However, the value of the evaluation step number signal DSN is 2 and theupper-limit voltage is 3.0V.

In a section T4-2, the power supply voltage transition comparisoncircuit 20C performs the lower-limit voltage evaluation step 2-2. Theoperation of the power supply voltage transition comparison circuit 20Cperformed in the section T4-2 is similar to that of the power supplyvoltage transition comparison circuit 20C in the section T2-2. However,the value of the evaluation step number signal DSN is 2 and thelower-limit voltage is 2.0V.

Since the power supply voltage PSV is lower than the upper-limit voltage3.0V and higher than the lower-limit voltage 2.0V, the voltageevaluation circuit 8C determines that the power supply voltage PSV iswithin the expected voltage range and notifies the voltage evaluationcontrol circuit 9B that the voltage evaluation result is “PASS” by usinga voltage evaluation result signal VDR (step S114). Meanwhile, the powersupply voltage supply apparatus keeps the power supply voltage PSVbetween the upper-limit voltage and the lower-limit voltage for the step2 in the sections T4-1 and T4-2.

The operation of the power supply voltage transition comparison circuit20C performed in the section T5 is similar to that of the power supplyvoltage transition comparison circuit 20C performed in the section T3.However, the voltage evaluation control circuit 9B increments the countvalue of the evaluation step counter 10 to three. The value of theevaluation step number signal DSN is 3 and the WAIT count value is 15.Further, the upper-limit voltage is 4.0V and the lower-limit voltage is3.0V. Meanwhile, the power supply voltage supply apparatus changes thepower supply voltage PSV from the voltage between the upper-limitvoltage and the lower-limit voltage for the step 2 to a voltage betweenthe upper-limit voltage and the lower-limit voltage for the step 3 (forexample, 3.5V).

In a section T6-1, the power supply voltage transition comparisoncircuit 20C performs the upper-limit voltage evaluation step 3-1. Theoperation of the power supply voltage transition comparison circuit 20Cperformed in the section T6-1 is similar to that of the power supplyvoltage transition comparison circuit 20C performed in the section T2-1.However, the value of the evaluation step number signal DSN is 3 and theupper-limit voltage is 4.0V.

In a section T6-2, the power supply voltage transition comparisoncircuit 20C performs the lower-limit voltage evaluation step 3-2. Theoperation of the power supply voltage transition comparison circuit 20Cperformed in the section T6-2 is similar to that of the power supplyvoltage transition comparison circuit 20C in the section T2-2. However,the value of the evaluation step number signal DSN is 3 and thelower-limit voltage is 3.0V.

Since the power supply voltage PSV is lower than the upper-limit voltage4.0V and higher than the lower-limit voltage 3.0V, the voltageevaluation circuit 8C determines that the power supply voltage PSV iswithin the expected voltage range and notifies the voltage evaluationcontrol circuit 9B that the voltage evaluation result is “PASS” by usinga voltage evaluation result signal VDR (step S114). Meanwhile, the powersupply voltage supply apparatus keeps the power supply voltage PSVbetween the upper-limit voltage and the lower-limit voltage for the step3 in the sections T6-1 and T6-2.

In a section T7, the voltage evaluation control circuit 9B incrementsthe count value of the evaluation step counter 10 to four, and outputsan evaluation step number signal DSN to the evaluation voltage settingvalue output circuit 7C, the transition number WAIT time setting circuit14, and the expected voltage setting circuit 15 and thereby conveys thecount value of the evaluation step counter 10 (=4) to them. Thetransition number WAIT time setting circuit 14 outputs a transitionnumber WAIT time setting signal TWS to the voltage evaluation controlcircuit 9B and thereby conveys a WAIT count value (=0) corresponding tothe value of the evaluation step number signal DSN (=4) to the voltageevaluation control circuit 9B. The expected voltage setting circuit 15outputs an expected voltage setting signal EVS to the evaluation voltagesetting value output circuit 7C and thereby conveys the values of theupper-limit voltage and the lower-limit voltage (=5.0V and 4.0V)corresponding to the value of the evaluation step number signal DSN (=4)to the evaluation voltage setting value output circuit 7C. Since theWAIT count value conveyed from the transition number WAIT time settingcircuit 14 is zero, the voltage evaluation control circuit 9B determinesthat the transition of the power supply voltage PSV matches the expectedvoltage transition and outputs a lock cancellation signal LCS.Meanwhile, the power supply voltage supply apparatus returns the powersupply voltage PSV to the normal voltage 5.0V.

According to this embodiment, the number of comparators can be reducedfrom two to one, thus making it possible to reduce the circuit size ofthe power supply voltage transition comparison circuit 20C. This isbecause by changing the voltage setting mode between the upper-limitvoltage setting mode in which the ratio K between the comparison voltageCV input to the comparator 3C and the power supply voltage PSV is setbased on the upper-limit voltage, and the lower-limit voltage settingmode in which the ratio K is set based on the lower-limit voltage, it ispossible to determine whether or not the power supply voltage PSV iswithin the expected voltage range based on the output of the comparator3C.

Note that in the step S106, when the power supply voltage PSV is higherthan the upper-limit voltage (when the comparator output signal CO is ata high level), the voltage evaluation circuit 8C may repeat thedetermination whether or not the power supply voltage PSV is lower thanthe higher-limit voltage. Further, either of the upper-limit voltageevaluation and the lower-limit voltage evaluation may be performedbefore the other voltage evaluation. In other words, the steps S108 toS112 may be performed after the steps S102 to S106 are performed.Alternatively, the steps S102 to S106 may be performed after the stepsS108 to S112 are performed. Further, the power supply voltage transitioncomparison circuit 20C may be configured so that the transition numberWAIT time setting circuit 14 and the expected voltage setting circuit 15are not used.

Fourth Embodiment

FIG. 12 is a circuit configuration diagram of a power supply voltagetransition comparison circuit 20D according to a fourth embodiment. Theconfiguration of the power supply voltage transition comparison circuit20D is different from that of the power supply voltage transitioncomparison circuit 20A in that the comparator evaluation voltage settingcircuit is disposed on the reference voltage side in the power supplyvoltage transition comparison circuit 20D. Further, the power supplyvoltage transition comparison circuit 20D does not include the BGRcircuit 2, while it includes a reference voltage output circuit 19.Further, the power supply voltage transition comparison circuit 20Dincludes a comparator evaluation voltage setting circuit 5D in place ofthe comparator evaluation voltage setting circuit 5 included in thecircuit 20A and includes comparators 3D and 4D in place of thecomparators 3 and 4 included in the circuit 20A.

The comparator evaluation voltage setting circuit 5D generates anupper-limit voltage ULV and a lower-limit voltage LLV as dividedvoltages of a reference voltage RV2. The comparator 3D compares theupper-limit voltage ULV with the power supply voltage PSV. Thecomparator 4D compares the lower-limit voltage LLV with the power supplyvoltage PSV. The voltage evaluation circuit 8 evaluates the power supplyvoltage PSV based on the result of the comparison between the powersupply voltage PSV and the upper-limit voltage ULV and the result of thecomparison between the power supply voltage PSV and the lower-limitvoltage LLV. The evaluation voltage setting value output circuit 7changes a ratio K3 between the reference voltage RV2 and the upper-limitvoltage ULV and a ratio K4 between the reference voltage RV2 and thelower-limit voltage LLV.

According to this embodiment, it is possible to increase the number ofexpected voltage levels, which are compared with the power supplyvoltage PSV, without increasing the number of comparators. This isbecause the ratio K3 between the reference voltage RV2 and theupper-limit voltage ULV and the ratio K4 between the reference voltageRV2 and the lower-limit voltage LLV are changed based on the result ofthe comparison between the power supply voltage PSV and the upper-limitvoltage ULV and the result of the comparison between the power supplyvoltage PSV and the lower-limit voltage LLV. Therefore, it is possibleto lower the probability of an accidental match between the transitionof the power supply Voltage PSV and the expected voltage transitionwhile minimizing the increase in the circuit size of the power supplyvoltage transition comparison circuit 20D.

Next, a configuration of the power supply voltage transition comparisoncircuit 20D is explained in detail.

The monitored power supply 1 outputs the power supply voltage, PSV tothe −input terminals of the comparators 3D and 4D. The reference voltageoutput circuit 19 outputs a reference voltage RV2 to the comparatorevaluation voltage setting circuit 5D. The reference voltage outputcircuit 19 keeps the reference voltage RV2 at a predetermined fixedvoltage. The reference voltage RV2 is preferably higher than the normalvoltage of the power supply voltage PSV. The comparator evaluationvoltage setting circuit 5D includes resistance voltage-dividing circuits12D and 13D. The resistance voltage-dividing circuit 12D generates anupper-limit voltage ULV from the reference voltage RV2 and outputs theupper-limit voltage ULV to the +input terminal of the comparator 3D. Theresistance voltage-dividing circuit 13D generates a lower-limit voltageLLV from the reference voltage RV2 and outputs the lower-limit voltageLLV to the +input terminal of the comparator 4D. The upper-limit voltageULV and the lower-limit voltage LLV are divided voltages of thereference voltage RV2.

The comparator evaluation voltage setting circuit 5D sets a ratio K3between the reference voltage RV2 and the upper-limit voltage ULV and aratio K4 between the reference voltage RV2 and the lower-limit voltageLLV at the same time based on the evaluation voltage setting signal DVS.Note that the evaluation voltage setting signal DVS indicates theupper-limit voltage and the lower-limit voltage of an expected voltagerange. The comparator evaluation voltage setting circuit 5D sets theresistance value of the resistance voltage-dividing circuit 12D andthereby sets the ratio K3 so that the upper-limit voltage ULV matchesthe upper-limit voltage indicated by the evaluation voltage settingsignal DVS. The comparator evaluation voltage setting circuit 5D setsthe resistance value of the resistance voltage-dividing circuit 13D andthereby sets the ratio K4 so that the lower-limit voltage LLV matchesthe lower-limit voltage indicated by the evaluation voltage settingsignal DVS. When the upper-limit voltage and the lower-limit voltageindicated by the evaluation voltage setting signal DVS change, thecomparator evaluation voltage setting circuit 5D changes the ratios K3and K4 so that they conform to the new upper-limit voltage andlower-limit voltage.

The comparator 3D performs a voltage upper-limit comparison. Thecomparator 3D compares the upper-limit voltage ULV input to the +inputterminal with the power supply voltage PSV input to the −input terminaland outputs a comparator output signal UCO, which is a digital signalindicating the comparison result, to the inverter-side input terminal ofthe inverter-equipped AND-gate 6. The comparator output signal UCO is ata low level when the power supply voltage PSV is lower than theupper-limit voltage ULV. Further, the comparator output signal UCO is ata high level when the power supply voltage PSV is higher than theupper-limit voltage ULV. In other words, when the power supply voltagePSV is lower than the upper-limit voltage indicated by the evaluationvoltage setting signal DVS, the comparator output signal UCO is at a lowlevel, whereas when the power supply voltage PSV is higher than theupper-limit voltage indicated by the evaluation voltage setting signalDVS, the comparator output signal UCO is at a high level.

The comparator 4D performs a voltage lower-limit comparison. Thecomparator 4D compares the lower-limit voltage LLV input to the +inputterminal with the power supply voltage PSV input to the −input terminaland outputs a comparator output signal LCO, which is a digital signalindicating the comparison result, to the other input terminal of theinverter-equipped AND-gate 6. The comparator output signal LCO is at alow level when the power supply voltage PSV is lower than thelower-limit voltage LLV. Further, the comparator output signal LCO is ata high level when the power supply voltage PSV is higher than thelower-limit voltage LLV. In other words, when the power supply voltagePSV is lower than the lower-limit voltage indicated by the evaluationvoltage setting signal DVS, the comparator output signal LCO is at a lowlevel, whereas when the power supply voltage PSV is higher than thelower-limit voltage indicated by the evaluation voltage setting signalDVS, the comparator output signal LCO is at a high level.

The configurations and the operations of the inverter-equipped AND-gate6, the voltage evaluation circuit 8, the evaluation voltage settingvalue output circuit 7, and the voltage evaluation control circuit 9 aresimilar to those in the first embodiment.

The power supply voltage transition comparison circuit 20D repeats theevaluation step while changing the ratio K3 between the referencevoltage RV2 and the upper-limit voltage ULV and the ratio K4 between thereference voltage VR2 and the lower-limit voltage LLV, and therebydetermines whether or not the transition of the power supply voltage PSVmatches the expected voltage transition. The evaluation step includesgenerating an upper-limit voltage ULV and a lower-limit voltage LLV fromthe reference voltage RV2, comparing the power supply voltage PSV withthe upper-limit voltage ULV, comparing the power supply voltage PSV withthe lower-limit voltage LLV, and determining whether or not the powersupply voltage PSV matches a predetermined expected voltage based on thecomparison results. When the power supply voltage PSV matches thepredetermined expected voltage, the power supply voltage transitioncomparison circuit 20D performs the next evaluation step.

Note that the control method for the power supply voltage transitioncomparison circuit 20D performed by the voltage evaluation controlcircuit 9 may be implemented by a computer that runs based on a computerprogram. The control method includes outputting an evaluation stepnumber signal DSN indicating a count value to the evaluation voltagesetting value output circuit 7, outputting a voltage evaluationimplementation instruction signal VDC to the voltage evaluation circuit8, and updating the count value based on a voltage evaluation resultsignal VDR.

Note that the comparator evaluation voltage setting circuit 5D generatesthe upper-limit voltage ULV and the lower-limit voltage LLV as dividedvoltages of the reference voltage RV2. The comparator 3D compares theupper-limit voltage ULV with the power supply voltage PSV. Thecomparator 4D compares the lower-limit voltage LLV with the power supplyvoltage PSV. When the voltage evaluation circuit 8 receives a voltageevaluation implementation instruction signal VDC, the voltage evaluationcircuit 8 evaluates the power supply voltage PSV based on the comparatoroutput signals UCO and LCO output from the comparators 3D and 4D andoutputs a voltage evaluation result signal VDR indicating the evaluationresult. The evaluation voltage setting value output circuit 7 sets theratio K3 between the reference voltage RV2 and the upper-limit voltageULV and the ratio K4 between the reference voltage RV2 and thelower-limit voltage LLV based on a predetermined setting valueassociated with the value of the evaluation step number signal DSN.

This embodiment may be combined with the second embodiment or combinedwith the third embodiment.

Fifth Embodiment

FIG. 13 is a schematic configuration diagram of a semiconductorintegrated circuit 50 according to a fifth embodiment. The semiconductorintegrated circuit 50 includes a power supply voltage transitioncomparison circuit 20, a lock control circuit 30, and a circuit 40 towhich access is protected (hereinafter called “access-protected circuit40”). The power supply voltage transition comparison circuit 20 may beany one of the power supply voltage transition comparison circuits 20Ato 20D. The power supply voltage transition comparison circuit 20determines whether or not the transition of the power supply voltage PSVmatches a predetermined expected voltage transition. Then, when thetransition of the power supply voltage PSV matches the predeterminedexpected voltage transition, the power supply voltage transitioncomparison circuit 20 outputs a lock cancellation signal LCS to the lockcontrol circuit 30. The lock control circuit 30 cancels the lock of theaccess-protected circuit 40 based on the lock cancellation signal LCS.

According to this embodiment, it is possible to cancel the lock of theaccess-protected circuit 40 based on the transition of the power supplyvoltage PSV.

Further, the above-described program can be stored in various types ofnon-transitory computer readable media and thereby supplied tocomputers. The non-transitory computer readable media includes various,types of tangible storage media. Examples of the non-transitory computerreadable media include a magnetic recording medium (such as a flexibledisk, a magnetic tape, and a hard disk drive), a magneto-optic recordingmedium (such as a magneto-optic disk), a CD-ROM (Read Only Memory), aCD-R, and a CD-R/W, and a semiconductor memory (such as a mask ROM, aPROM (Programmable ROM), an EPROM (Erasable PROM), a flash ROM, and aRAM (Random Access Memory)). Further, the program can be supplied tocomputers by using various types of transitory computer readable media.Examples of the transitory computer readable media include an electricalsignal, an optical signal, and an electromagnetic wave. The transitorycomputer readable media can be used to supply programs to computerthrough a wire communication path such as an electrical wire and anoptical fiber, or wireless communication path.

The present invention made by the inventor has been explained above in aspecific manner based on embodiments. However, the present invention isnot limited to the above-described embodiments, and needless to say,various modifications can be made without departing from the spirit andscope of the present invention.

Further, a part of the contents described above in the embodiments isdescribed below.

(1) A power supply voltage transition comparison method includesrepeating an evaluation step while changing a ratio between a dividedvoltage of one of a power supply voltage and a reference voltage and theone voltage, and thereby determining whether or not a power supplyvoltage transition matches an expected voltage transition. Theevaluation step includes generating the divided voltage from the onevoltage, comparing the other of the power supply voltage and thereference voltage with the divided voltage, and determining whether ornot the power supply voltage matches an expected voltage based on thecomparison result between the other voltage and the divided voltage. Thepower supply voltage transition comparison method includes performing anext evaluation step when it is determined that the power supply voltagematches the expected voltage.(2) The power supply voltage transition comparison method described inthe item (1) further includes arbitrarily setting the expected voltagetransition.(3) The power supply voltage transition comparison method described inthe item (1) further includes arbitrarily setting a wait time betweenthe evaluation steps.(4) The power supply voltage transition comparison method described inthe item (1) further includes arbitrarily setting the number of timesthat the evaluation step is repeated.(5) The power supply voltage transition comparison method described inthe item (1) further includes arbitrarily setting the expected voltagein each evaluation step.(6) A program that causes a computer to execute a control method for apower supply voltage transition comparison circuit. The power supplyvoltage transition comparison circuit includes a comparator evaluationvoltage setting circuit, a comparator, a voltage evaluation circuit, andan evaluation voltage setting value output circuit. The comparatorevaluation voltage setting circuit generates a divided voltage of one ofa power supply voltage and a reference voltage. The comparator comparesthe other of the power supply voltage and the reference voltage with thedivided voltage. When the voltage evaluation circuit receives a voltageevaluation implementation instruction signal, the voltage evaluationcircuit evaluates the power supply voltage based on an output of thecomparator and outputs a voltage evaluation result signal indicating aresult of an evaluation of the power supply voltage. The evaluationvoltage setting value output circuit sets a ratio between the onevoltage and the divided voltage based on a predetermined setting valueassociated with a value of an evaluation step number signal. The controlmethod includes outputting an evaluation step number signal indicating acount value to the evaluation voltage setting value output circuit,outputting a voltage evaluation implementation instruction signal to thevoltage evaluation circuit, and updating the count value based on avoltage evaluation result signal.(7) In the program described in the item (6), the control method furtherincludes securing a predetermined wait time from when the evaluationstep number signal is output to when the voltage evaluationimplementation instruction signal is output.(8) In the program described in the item (6), the control method furtherincludes outputting a lock cancellation signal indicating a cancellationof a lock of an access-protected circuit when the count value is a lastvalue and the voltage evaluation result signal indicates that the powersupply voltage is within an expected voltage range.

The first to fifth embodiments can be combined as desirable by one ofordinary skill in the art.

While the invention has been described in terms of several embodiments,those skilled in the art will recognize that the invention can bepracticed with various modifications within the spirit and scope of theappended claims and the invention is not limited to the examplesdescribed above.

Further, the scope of the claims is not limited by the embodimentsdescribed above.

Furthermore, it is noted that, Applicant's intent is to encompassequivalents of all claim elements, even if amended later duringprosecution.

What is claimed is:
 1. A power supply voltage transition comparisoncircuit comprising: a comparator evaluation voltage setting circuit thatgenerates a divided voltage of a power supply voltage; a comparator thatcompares a reference voltage with the divided voltage; a voltageevaluation circuit that evaluates the power supply voltage based on aresult of the comparison; and an evaluation voltage setting value outputcircuit that changes a ratio between the power supply voltage and thedivided voltage based on a result of an evaluation of the power supplyvoltage.
 2. The power supply voltage transition comparison circuitaccording to claim 1, wherein the evaluation voltage setting valueoutput circuit changes a voltage setting mode between an upper-limitvoltage setting mode in which the ratio between the power supply voltageand the divided voltage is set based on an upper-limit voltage of anexpected voltage range, and a lower-limit voltage setting mode in whichthe ratio between the power supply voltage and the divided voltage isset based on a lower-limit voltage of the expected voltage range basedon an upper/lower selector signal output by the voltage evaluationcircuit, and the voltage evaluation circuit determines whether or notthe power supply voltage is within the expected voltage range based onan output of the comparator.
 3. The power supply voltage transitioncomparison circuit according to claim 2, wherein the voltage evaluationcircuit secures a predetermined wait time after the voltage evaluationcircuit changes the upper/lower selector signal from a value indicatingone of the upper-limit voltage setting mode and the lower-limit voltagesetting mode to a value indicating the other of the upper-limit voltagesetting mode and the lower-limit voltage setting mode, and thendetermines whether the power supply voltage is lower than theupper-limit voltage or determines whether the power supply voltage ishigher than the lower-limit voltage based on the output of thecomparator.
 4. The power supply voltage transition comparison circuitaccording to claim 1, wherein the evaluation voltage setting valueoutput circuit changes a voltage setting mode between an upper-limitvoltage setting mode in which the ratio between the power supply voltageand the divided voltage is set based on an upper-limit voltage of anexpected voltage range, and a lower-limit voltage setting mode in whichthe ratio between the power supply voltage and the divided voltage isset based on a lower-limit voltage of the expected voltage range basedon an upper/lower selector signal output by the voltage evaluationcircuit.
 5. The power supply voltage transition comparison circuitaccording to claim 1, wherein the voltage evaluation circuit determineswhether or not the power supply voltage is within an expected voltagerange based on an output of the comparator.
 6. A power supply voltagetransition comparison method, comprising: generating a divided voltageof a power supply; comparing a reference voltage with the dividedvoltage; evaluating the power supply voltage based on a result of thecomparison; and changing a ratio between the power supply voltage andthe divided voltage based on a result of an evaluation of the powersupply voltage.
 7. The power supply voltage transition comparison methodaccording to claim 6, further comprising changing, by a voltageevaluation circuit, a voltage setting mode between an upper-limitvoltage setting mode and a lower-limit voltage setting mode, wherein: inthe upper-limit voltage setting mode, a ratio between the power supplyvoltage and the divided voltage is set based on an upper-limit voltageof an expected voltage range; in the lower-limit voltage setting mode,the ratio between the power supply voltage and the divided voltage isset based on a lower-limit voltage of the expected voltage range; andthe evaluating of the power supply voltage comprises evaluating, by thevoltage evaluation circuit, whether or not the power supply voltage iswithin the expected voltage range based on an output of a comparatorthat compares the reference voltage with the divided voltage.
 8. Thepower supply voltage transition comparison method according to claim 6,further comprising changing, by a voltage evaluation circuit, a voltagesetting mode between an upper-limit voltage setting mode and alower-limit voltage setting mode.
 9. The power supply voltage transitioncomparison method according to claim 8, wherein: in the upper-limitvoltage setting mode, a ratio between the power supply voltage and thedivided voltage is set based on an upper-limit voltage of an expectedvoltage range.
 10. The power supply voltage transition comparison methodaccording to claim 8, wherein: in the lower-limit voltage setting mode,the ratio between the power supply voltage and the divided voltage isset based on a lower-limit voltage of the expected voltage range; andthe evaluating of the power supply voltage comprises evaluating, by thevoltage evaluation circuit, whether or not the power supply voltage iswithin the expected voltage range based on an output of a comparatorthat compares the reference voltage with the divided voltage.
 11. Apower supply voltage transition comparison circuit, comprising: acomparator evaluation voltage setting circuit that generates a dividedvoltage based on a power supply voltage; a comparator that compares areference voltage with the divided voltage; a voltage evaluation circuitthat evaluates the power supply voltage based on a result of thecomparison; and an evaluation voltage setting value output circuit thatoutputs an evaluation voltage setting signal base on a result of theevaluation, wherein the comparator evaluation voltage setting circuitgenerates the divided voltage based on the evaluation voltage settingsignal.
 12. The power supply voltage transition comparison circuitaccording to claim 11, wherein the comparator evaluation voltage settingcircuit comprises: a resistance voltage-dividing circuit that generatesthe comparison voltage by dividing the power supply voltage.
 13. Thepower supply voltage transition comparison circuit according to claim11, wherein the comparator evaluation voltage setting circuit sets, whenthe evaluation voltage setting signal indicates the upper-limit voltageof an expected voltage range, the ratio so that when the power supplyvoltage matches the upper-limit voltage, the comparison voltage matchesthe reference voltage, and the comparator evaluation voltage settingcircuit sets, when the evaluation voltage setting signal indicates thelower-limit voltage of the expected voltage range, the ratio so thatwhen the power supply voltage matches the lower-limit voltage, thecomparison voltage matches the reference voltage.
 14. The power supplyvoltage transition comparison circuit according to claim 11, wherein theresult of the comparison is a low level signal when the comparisonvoltage is lower than the reference voltage, and is a high level signalwhen the comparison voltage is higher than the reference voltage. 15.The power supply voltage transition comparison circuit according toclaim 11, wherein the result of the comparison is a low level signalwhen the power supply voltage is lower than the voltage indicated by theevaluation voltage setting signal, and is a high level signal when thepower supply voltage is higher than the voltage indicated by theevaluation voltage setting signal, and the comparator output signal isat a high level.
 16. The power supply voltage transition comparisoncircuit according to claim 11, wherein the voltage evaluation circuitdetermines whether or not the power supply voltage is lower than theupper-limit voltage of the expected voltage range based on the result ofthe comparison in a first mode, and determines whether or not the powersupply voltage is higher than the lower-limit voltage of the expectedvoltage range based on the comparison in a second mode.
 17. The powersupply voltage transition comparison circuit according to claim 13,wherein the voltage evaluation circuit determines that the power supplyvoltage is within the expected voltage range when the power supplyvoltage is lower than the upper-limit voltage and higher than thelower-limit voltage.
 18. The power supply voltage transition comparisoncircuit according to claim 16, wherein: the voltage evaluation circuitoutputs a mode selector signal; and the comparator evaluation voltagesetting circuit changes the voltage setting mode between the first modeand the second mode based on the mode selector signal.
 19. The powersupply voltage transition comparison circuit according to claim 16,wherein the evaluation voltage setting value output circuit notifies thecomparator evaluation voltage setting circuit of the upper-limit voltagein the first mode, and notifies the comparator evaluation voltagesetting circuit of the lower upper-limit voltage in the second mode.